1. Field of the Invention
The present invention is generally related to flash memory systems. More particularly, the invention relates to a compact flash controller that manages a set of compact flash memory modules used as a storage device, and/or an external memory device having a flash memory as a storage medium.
2. Description of the Related Art
Many of the smaller electronic devices and systems such as digital cameras, MPEG portable music system, and personal data assistants are now being configured with memory designed to store both data and applications content captured by these devices. One advantage of having memory in such devices is that the captured data or application content can be eventually downloaded to a host system at a subsequent time. For example, a digital camera captures an array of images and stores them in memory to be downloaded to an image or graphics application program running on a computer system that coverts the captured images into high-resolution photographs that can be incorporated in newspaper and magazine articles or a presentation.
Typically, these devices employ a non-volatile, readable/writable storage device that requires very little, if any, power to retain its content. This solid state or semiconductor data storage system, commonly referred as a flash memory is a card that incorporates a controller, plurality of flash memory modules or arrays, and a PCMCIA interface that provides the required connectivity to an electronic device or system. Each module includes a number of flash memory cells that are organized in a set of independently erasable blocks. The controller performs the fundamental operation of read, write, and block erase to stores either data or application content in one or more memory locations and then recalls the stored data or application content, upon request, for output to an external device or system. Unlike other forms of memory or mass storage, the amount of time necessary to perform a write data or program bit and erase can be significant. Nevertheless, for a number of applications, the advantages of low power, ruggedness, portability and smaller size of a flash memory system makes it a reasonable alternative to other data storage devices.
FIG. 1 is a block diagram illustrating a typical flash memory controller as implemented in the prior art. FIG. 1 shows that the flash memory controller 104 comprises a host interface 110 that includes a host multiplexer 116, a buffer manager 112 that has a buffer multiplexer 118, and a flash memory formatter 114 comprising a flash memory sequencer 120 and an ECC process circuit 122 to perform error correction. The host interface 110 transfers data, commands and or application content to and from the host computer 102. The host multiplexer 116 operates on time division basis to convert the received data, commands or application content in a sixteen bit format into an eight bit format prior to it being stored in one or more flash memory arrays 108. In addition, the host multiplexer 116 converts the data, commands or application content retrieved from flash memory 108 into a sixteen bit data stream so it can be transmitted back to the host computer 102 for processing.
As shown by FIG. 1, the flash memory controller 104 uses an external buffer 106 to execute all of the read/write operations between the host system 102 and the flash memory 108. Thus, when data is to be written to flash memory 108, the data, commands or application content received from the host computer 102 is converted from a sixteen bit to a eight bit data stream by the host interface 110 and is then placed in the external data buffer 106 by the buffer memory manager 112. Once stored in the buffer 106, the data is directed through the buffer memory multiplexer 118 of the buffer manager 112 to the flash memory formatter 114. The flash memory sequencer 120 controls an access process of writing to and or reading from one or more sectors of the flash memory 108. Under program control, the flash memory sequencer 120 transfers data or application content, via an eight-bit bus, to and from one or more sectors of the flash memory 108. As described above, all data movement or transfer functions between the host system 102 and the flash memory 108 must pass through the buffer multiplexer 118 and external buffer 106. This is due to the fact that the transfer rate of flash memory 108 is much slower than that of host computer 102. In other words, in order to perform either a write to, read from, or erase the contents function, the eight bit bus 124 between the flash memory controller 104 and flash memory 108 is occupied for a substantial period of time. Here, the external buffer 106 is used to equalize the differences in the transfer rate between the host system 102 and flash memory 108 by allowing data or application content to be transmitted to and received from host computer 102 more efficiently.
The problem with this approach is that it takes twice as long to transfer data or applications content in or out of flash memory 108 when all data transfer functions must be passed through the buffer manager 112 as well as in and out of the external buffer 106. By using an external buffer each and every time to perform a write cycle or read cycle via the buffer, it reduces the overall performance of the flash memory controller. In addition, a flash memory controller of this type is limited to transmitting the stored commands, data or application content through a single input-output interface. As a result, electronic devices that incorporate such a mechanism are only able to download data to external sources through the host interface. Hence, an external source such as a digital camera, MPEG portable player, or personal data assistant that receives the stored data and or application content via a flash memory system with this type of controller has to have the same or similar interface to receive the data from the memory.
Hence, there is a need for a compact flash memory controller that can be constructed at a cost comparable to that of currently available flash memory modules. In addition, the needed compact flash memory controller should incorporate and support other capabilities in a manner that would allow for simple transmission of data stored in the flash memory via one or more industry standard I/O interfaces. The needed compact flash controller should utilize interface to a variety of different devices in a variety of configurations such as a PCMCIA-ATA and IDE modes. Each of these modes of operation requires different protocols. Upon initialization with an interface device, this needed compact flash controller should automatically detect which operation mode is used by this interface device and configure the memory card to be compatible with its operation.
An object of the present invention is to provide a new and improved compact flash memory controller by overcoming at least some of the disadvantages and limitations of flash memory controller as implemented in the prior art.
It is also an object of the present invention to provide a compact flash controller that provides a means for writing to and reading data from a plurality of flash memory modules with improved throughput characteristics.
The above and other objects are attained by a compact flash memory controller in accordance with this invention for controlling transfer of data between flash memory and a host device comprising:
A PCMCIA-ATA flash memory interface, an IDE interface, a microcontroller, a ROM memory for program storage, a RAM memory for program execution and to maintain a set of command and attribute registers used by the microcontroller to manage the data transfer operation in and out of a plurality of flash memory, a buffer manager for temporarily storing data to be transferred to and from flash memory, a flash memory sequencer for controlling the transfer of a data to and from flash memory that has been received from the buffer manager and a data bus couple to the set of operative components that include the microcontroller, the PCMCIA-ATA flash memory interface, the IDE interface, the ROM memory, the RAM memory and the buffer manager.